View MC141803_728888.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
LCD Segment / Common Driver with Controller
CMOS
MC141803 is a CMOS LCD Driver which consists of 4 annunciator outputs and 153 high voltage LCD driving signals (33 commons and 120 segments). MC141803 is split common output design. It has parallel interface capability for operating with general MCU. Besides the general LCD driver features, it has an on chip LCD bias Voltage Generator circuit such that fewer external components are required during application. * * * * * * * * * * * * * * * * * * * Single Supply Operation, 2.4 V - 3.5 V Operating Temperature Range : -30 to 85C Low Current Stand-by Mode (<500nA) On Chip Bias Voltage Generator 8 Bit Parallel Interface Graphic Mode Operation On Chip 120 x 33 Graphic Display Data RAM 120 Segment Drivers, 33 Common Drivers Selectable 1/16, 1/32, 1/33 Multiplex Ratio Selectable on Chip Voltage Doubler and Tripler Selectable 1:5 or 1:7 Bias Ratio Re-mapping of Row and Column Drivers Four Stand Alone Annunciator (Static Icon) Driver Circuits Low Power Icon Mode Driven by Com32 in Special Driving Scheme Selectable LCD Driving Voltage Temperature Coefficients 16 Level Internal Contrast Control External Contrast Control Provided Master Clear RAM Standard TAB Package
MC141803
MC141803T TAB
ORDERING INFORMATION
MC141803T
TAB
REV 4 2/98
MOTOROLA
MC141803 3-313
Block Diagram
BP
Annun0 to Annun3
Com0 to Com32
Seg0~Seg119
Annunciator Control Circuit
HV Buffer Cell Level Shifter
Level Selector
VLL6 33 Bit Latch OSC1 OSC2 Display Timing Generator VLL2 VCC VR VF LCD Driving Voltage Generator Tripler, Doubler, Voltage Regulator, Voltage Divider, Contrast Control, Temperature Compensation C2P C2N C1P C1N DUM2 DUM1 C+ CAVDD AVSS
120 Bit Latch
GDDRAM 33 X 120 Bits
Command Decoder
DVSS DVDD Command Interface Parallel Interface
RES
D/C
CS (CLK)
CE
R/W
D0~D7
MC141803 3-314
MOTOROLA
MOTOROLA
DUMMY DUMMY DVSS OSC1 AVSS VR VF VCC CC+ DUM2 OSC2 DUM1 VLL6 VLL5 VLL4 VLL3 VLL2 C2N C2P C1N C1P AVDD DVSS CE D7 D6 D5 D4 D3 D2 D1 D0 DVSS CS(CLK) R/W D/C DVSS RES DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 DUMMY . . 63 62 61 60 59 58 57 56 . . . . 47 46 45 44 43 42 41 40 39 197 196 195 194 193 192 . . . . . 184 183 182 181 180 179 178 177 176 . . . . . . . . . COM32 COM0 COM1 COM2 COM3 COM4 . . . . . COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 . . . . . . . . . . . . SEG117 SEG118 SEG119 COM32 COM31 COM30 COM29 COM28 . . . . COM19 COM18 COM17 COM16 ANNUN0 ANNUN1 ANNUN2 ANNUN3 BP
MC141803T PIN ASSIGNMENT
(COPPER VIEW)
DUMMY
MC141803 3-315
MAXIMUM RATINGS* (Voltages Referenced to VSS, TA=25C)
Symbol AVDD,DVDD VCC Vin I TA Tstg Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range Supply Voltage Parameter Value -0.3 to +4.0 VSS-0.3 to VSS+10.5 VSS-0.3 to VDD+0.3 25 -30 to +85 -65 to +150 Unit V V V mA C C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. VSS = AVSS = DVSS (DVSS = VSS of Digital circuit, AVSS = VSS of Analogue Circuit) VDD = AVDD = DVDD (DVDD = VDD of Digital circuit, AVDD = VDD of Analogue Circuit)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, TA=25C)
Symbol VDD IAC Parameter Supply voltage (Absolute value Referenced to VSS) AVDD=DVDD Test Condition Min 2.4 0 Typ 3.15 200 Max 3.5 300 Unit V A A A
IDP1
IDP2
ISB1 ISB2 ISB3 IICON
Supply Current (Measure with VDD fixed at 3.15V) Access Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Tripler and DVDD. Enable, R/W Accessing, Tcyc=1MHz, Osc. Freq.=50kHz, 1/33 Duty Cycle,1/7 Bias. Display Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Tripler and DVDD. Enable, R/W Halt, Osc. Freq.=50kHz, 1/33 Duty Cycle,1/7 Bias. Display Mode Supply Current Drain from Pin AVDD Internal DC/DC Converter On, Display On, Tripler and DVDD Enable, R/W Halt, Osc. Freq.=38.4kHz, 1/33 Duty Cycle,1/7 Bias. Stand-by Mode Supply Current Drain from Pin Display Off, Oscillator Disabled, R/W Halt AVDD and DVDD Stand-by Mode Supply Current Drain from Pin Display Off, Oscillator Enable, R/W Halt, External AVDD and DVDD. Oscillator and Frequency = 50kHz. Stand-by Mode Supply Current Drain from Pin Display Off, Oscillator Enable, R/W Halt, Internal AVDD and DVDD. Oscillator and Frequency = 50kHz. Stand-by Mode Supply Current Drain from Pin Low Power Icon Mode, Oscillator Enable, R/W AVDD and DVDD Halt, Internal Oscillator and Frequency = 50kHz VLCD Voltage (Absolute Value Referenced to VSS) LCD Driving Voltage Generator Output Voltage at Pin VCC. LCD Driving Voltage Generator Output Voltage at Pin VCC. LCD Driving Voltage input at pin VCC. Output Voltage Output High Voltage at Pins D0-D7, Annun0-3, BP and OSC2. Output Low Voltage at Pins D0-D7, Annun0-3, BP and OSC2. LCD Driving Voltage Source at Pin VR LCD Driving Voltage Source at Pin VR Input Voltage Input High Voltage at Pins RES, CE, CS, D0-D7, R/W, D/C, OSC1 and OSC2. Input Low Voltage at Pins RES, CE, CS, D0-D7, R/ W, D/C, OSC1 and OSC2. Display On, Internal DC/DC Converter Enabled, Tripler Enable, Osc. Freq. = 50kHz, Regulator Enabled, Divider Enabled Iout <= 100A Display On, Internal DC/DC Converter Enabled, Doubler Enable, Osc. Freq. = 50kHz, Regulator Enabled, Divider Enabled Iout <= 100A Internal DC/DC Converter Disabled. Iout=100A Iout=100A Regulator Enabled, Iout=50A Regulator Disabled
0
80
150
0
60
100
0 0 0 -
300 2.5 5 15
500 5 10 25
nA A A A
VCC1
-
3*DVDD
10.5
V
VCC2
-
2*DVDD
7
V
VLCD VOH1 VOL1 VR1 VR2 VIH1 VIL1
5 0.8*VDD 0 0 0.8*VDD 0
Floating -
10.5 VDD 0.2*VDD VCC VDD 0.2*VDD
V V V V V V V
MC141803 3-316
MOTOROLA
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, DVDD=2.4-3.15V, TA=25C)
Symbol VLL6 VLL5 VLL4 VLL3 VLL2 VLL6 VLL5 VLL4 DUM2 DUM1 VLL3 VLL2 VLL6 VLL5 VLL4 VLL3 VLL2 IOH IOL IOZ IIL/IIH Ron Output Current Output High Current Source from Pins D0-D7, Annun0-3, BP and OSC2 Output Low Current Drain by Pins D0-D7, Annun0-3, BP and OSC2 Output Tri-state Current Drain Source at pins D0D7 and OSC2 Input Current at pins RES, CE, CS, D0-D7, R/W, D/C OSC1 and OSC2. On Resistance Channel Resistance between LCD Driving Signal Pins (SEG and COM) and Driving Voltage Input Pins (VLL2 to VLL6). Memory Retention Voltage (DVDD) Standby Mode, Retained All Internal Configuration and RAM Data Input Capacitance All Control Pins Temperature Coefficient Compensation Flat Temperature Coefficient Temperature Coefficient 1* Temperature Coefficient 2* Temperature Coefficient 3* Internal Contrast Control VR Output Voltage with Internal Contrast Control Selected. 16 Voltage Levels Controlled by Software. Each Level is Typical of 2.25% of the Regulator Output Voltage. TC1=0, TC2=0, Voltage Regulator Disabled. TC1=0, TC2=1, Voltage Regulator Enabled. TC1=1, TC2=0, Voltage Regulator Enabled. TC1=1, TC2=1, Voltage Regulator Enabled. Internal Regulator Enabled, Internal Contrast Control Enabled. During Display on, 0.1V Apply between Two Terminals, VCC within Operating Voltage Range. Parameter LCD Display Voltage. (LCD Driving Voltage Output from Pins VLL6, VLL5, VLL4, VLL3 and VLL2.) Test Condition 1/5 Bias Ratio, Voltage Divider Enabled, Regulator Enabled. Min 0.5VCC 0.5VCC 0.5VCC VSS VSS 100 -1 -1 Typ VR 0.8*VR 0.6*VR 0.4*VR 0.2*VR VR 6/7*VR 5/7*VR 4/7*VR 3/7*VR 2/7*VR 1/7*VR Max VCC VCC VCC 0.5VCC 0.5VCC -100 1 1 10 Unit V V V V V V V V V V V V V V V V V A A A A k
1/7 Bias Ratio, Internal Voltage Divider Enabled, Regulator Enabled
External Voltage Generator, Internal Voltage Divider Disable
Vout=VDD-0.4V. Vout=0.4V.
VSB
1.8
-
-
V
CIN
-
5
7.5
pF
PTC0 PTC1 PTC2 PTC3 VCN
-
0.0 -0.18 -0.22 -0.35 18
-
% % % % %
* The formula for the temperature coefficient is: 1 VR at 50C - VR at 0C TC(%)= X100% X VR at 25C 50C - 0C
MOTOROLA
MC141803 3-317
Total variation of VR VRT is affected by the following factors : Process variation of Regulator VR External VDD Variation contributed to Regulator VVDD External resistor pair Ra/Rf contributed to Regulator Vres where V RT =
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, AVDD=DVDD=2.4 to 3.5V, TA=25C)
( V R ) + ( V V
2
DD
) + ( V res )
2
2
Assume external VDD variation is 6% at 3.15V and 1% variation resistor used at application TC Level Reference Generator TC0 TC1 TC2 TC3 VVDD (%) 6.0 4.0 2.5 1.4 VR (%) 2.5 Vres (%) 1.414 VRT (%) 6.652 4.924 3.805 3.195
AC ELECTRICAL CHARACTERISTICS (TA=25C, Voltage referenced to VSS, VDD=2.4 to 3.15V)
Symbol Parameter FOSC1 FANN1 FFRM1 Test Condition Min Typ 38.4 18.75 Max Unit kHz Hz
FCON1
Oscillation Frequency. Set Clock Frequency to Slow Oscillation Frequency of Display Timing Generator with 60Hz Frame Frequency. Annunciator Display (50% duty cycle) from Pins Annun0-3 and BP LCD Driving Signal Frame Frequency. Either External Clock Input or Internal Oscillator Enable, Either 1/32 or 1/16 Duty Cycle, Graphic Display Mode. LCD Driving Signal Frame Frequency. Either External Clock Input or Internal Oscillator Enable, 1/33 Duty Cycle, Graphic Display Mode. Oscillation Freq. Set Clock Frequency to Normal Oscillation Frequency of Display Timing Generator with 60Hz Frame Frequency. Annunciator Display Frequency (with 50% duty cycle) from Pins Annun0-3 and BP LCD driving Signal Frame Frequency. Either External Clock Input or Internal Oscillator Enable, Either 1/32 or 1/16 Duty Cycle. LCD driving Signal Frame Frequency. Either External Clock Input or Internal Oscillator Enable, 1/33 Duty Cycle. Internal Oscillation Frequency Internal Oscillator Enabled. VDD within Operation Internal OSC Oscillation Frequency with Different Range. Value of Feedback Resistor.
-
66 64
-
Hz Hz
Fosc2 FANN2 FFRM2 FCON2 OSC
-
50 24.4 65 63
-
kHz Hz Hz Hz
See Figure 1 for the relationship
Set Clock Frequency to Slow : FFRM1=FOSC1/576 Set Clock Frequency to Normal : FFRM2=FOSC2/768
MC141803 3-318
MOTOROLA
220k 200k 90k 70k Oscillation Frequency (Hz) 50k 30k 10k 100k 500k 1.0M 1.5M 2.0M Resistor Value between OSC1 and OSC2 ()
Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value
AC OPERATION CONDITIONS AND CHARATERISTICS ELECTRICAL CHARACTERISTICS LCD Panel driving signal timing (TA=-30 to 85C, VDD = 2.4 to 3.5V, VSS = 0V)
1
2
3
4
1
2
3
4
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1
COMx
SEGy
1/FANN
BP, Annun0-3
Figure 2. LCD Driving Signal Timing Diagram
MOTOROLA
MC141803 3-319
TABLE 2a. Parallel Timing Characteristics (Write Cycle) (TA=-30 to 85C, DVDD=2.4 to 3.5V, VSS=0V)
Symbol tcycle tEH tAS tDS tDH tAH Enable Cycle Time Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Parameter Min 600 290 5 290 20 20 Typ Max Unit ns ns ns ns ns ns
CE tcycle
CS tEH
R/W tAS D/C tDS D0-D7 Valid Data tDH tAH
Figure 3. Timing Characteristics (Write Cycle)
MC141803 3-320
MOTOROLA
TABLE 2b. Parallel Timing Characteristics (Read Cycle) (TA=-30 to 85C, DVDD=2.4 to 3.5V, VSS=0V)
Symbol tcycle tEH tAS tDS tDH tAH Enable Cycle Time Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Parameter Min 600 290 5 10 20 Typ Max 290 Unit ns ns ns ns ns ns
CE tcycle
CS tEH
R/W tAS D/C tDS D0-D7 tDH Valid Data tAH
Figure 4. Timing Characteristics (Read Cycle)
MOTOROLA
MC141803 3-321
PIN DESCRIPTIONS
D/C (Data / Command) This input pin let the driver distinguish the input at D0-D7 is data or command. Input High for data while input Low for command. CS (CLK) (Chip Select / Input Clock) This pin is normal Low clock input. Data on D0-D7 is latched at the falling edge of CS. RES (Reset) An active Low pulse to this pin reset the internal status of the driver (same as power on reset). The minimum pulse width is 10 s. CE (Chip Enable) HIGH input to this pin to enable the control pins on the driver. D0-D7 This bi-directional bus is used for data / command transferring. R/W (Read/Write) This is an input pin. To read the display data RAM or the internal status (Busy / Idle), pull this pin High. The R/W input Low indicates a write operation to the display data RAM or to the internal setup registers. OSC1 (Oscillator Input) For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In this mode, an external resistor of certain value is placed between the OSC1 and OSC2 pins for a range of internal operating frequencies (refer to Figure 1). For external oscillator mode, OSC1 should be left open. OSC2 (Oscillator Output / External Oscillator Input) This is an output for the internal low power RC oscillator circuit. For external oscillator mode, OSC2 will be an input pin for external clock and no external resistor is needed. VLL6 - VLL2 Group of voltage level pins for driving the LCD panel. They can either be connected to external driving circuit for external bias supply or connected internally to built-in divider circuit. For internal Voltage Divider enabled, a 0.1F capacitor to AVSS is required on each pin. DUM1 and DUM2 If internal Voltage Divider is enabled with 1/7 bias selected, a capacitor to AVSS is required on each pin. Otherwise, pull these two pin to AVSS C1N and C1P If Internal DC/DC Converter is enabled, a capacitor is required to connect these two pins. C2N and C2P If internal Tripler is enabled, a capacitor is required between these two pins. Otherwise, leave these pin open.
C+ and CIf internal divider circuit is enabled, a capacitor is required to connect between these two pins. VR and VF This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For adjusting the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a gain control resistor placed between VF and AVSS, a 10 F capacitor placed between VR and AVSS. (Refer to the Application Circuit) COM0-COM32 (Row Drivers) These pins provide the row driving signal to LCD panel. Com0Com31 are used in 32 mux configuration. Com0-Com15 are used in 16 mux and no row remap configuration while Com16-Com31 are used in 16 mux with row remap configuration. Com32 is used to drive the non-static icons in 33 Mux. They output 0V during display off. (Note : The IC facilitates two Com32 pins, which output same signal, for the LCD panel layout flexibility.) SEG0-SEG119 (Column Drivers) These 120 pins provide LCD column driving signal to LCD panel. They output 0V during display off. BP (Annunciator Backplane) This pin combines with Annun0-Annun3 pins to form annunciator driving part. When the annunciator circuit is enabled, it will output square wave of FANNn Hz. It outputs low when oscillator is disabled. Annun0 - Annun3 (Annunciator Frontplanes) These pins are four independent annunciator driving outputs. The enabled annunciator outputs from its corresponding pin a FANNn Hz square wave which is 180 degrees out of phase with BP. Disabled annunciator output from its corresponding pin an square wave inphase with BP. When oscillator is disabled, all these pins output 0V. AVDD and AVSS AVDD is the positive supply to the noise sensitive circuitry in LCD Driver and should be at same level as DVDD. AVSS is ground. VCC For using the Internal DC/DC Converter, a 0.1 F capacitor from this pin to AVSS is required. It can also be an external bias input pin if Internal DC/DC Converter is not used. Positive power is supplied to the LCD Driving Level Selector and HV Buffer Cell with this pin. Normally, this pin is not intended to be a power supply to other component. DVDD and DVSS Power is supplied to the digital control circuit and other circuitry in LCD bias Voltage Generator of the driver using these two pins. DVDD is power and DVSS is ground.
MC141803 3-322
MOTOROLA
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module
Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C high, data is written to Graphic Display Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is interpreted as a Command. CE is the master chip selection signal. A High input enable the input lines ready to sample signals. Reset is of same function as Power ON Reset (POR). Once RES received the reset pulse, all internal circuitry will back to its initial status. Refer to Command Description section for more information. MPU Parallel Interface The parallel interface consists of 8 bi-directional data lines (D0D7), R/W, and the CS. The R/W input High indicates a read operation from the Graphic Display Data RAM (GDDRAM). R/W input Low indicates a write to Display Data RAM or Internal Command Registers depending on the status of D/C input. The CS input serves as data latch signal (clock). Refer to AC operation conditions and characteristics section for Parallel Interface Timing Description. Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is determined by number of row times the number of column (120x33 = 3960 bits). Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided.
Column address 00H (or column address 77H)
Column address 77H (or column address 00H)
Row 0
LSB
Com0 (Com31)
Page 1
MSB LSB
Page 2 MSB LSB
Page 3 MSB LSB
Page 4 MSB LSB Note : The configuration in parentheses represents the remapping of Row and Columns Seg119 Seg0
Row 31 Page 5 Row 32
Com31 (Com0) Com32
Figure 5. Graphic Display Data RAM (GDDRAM) Address Map
MOTOROLA
MC141803 3-323
Display Timing Generator This module is an on chip low power RC oscillator circuitry (Figure 6). The oscillator frequency can be selected in the range of 15 kHz to 50 kHz by external resistor. One can enable the circuitry by software command. For external clock provided, feed the clock to OSC2 and leave OSC1 open.
Annunciator Control Circuit The LCD waveform of the 4 annunciators and BP are generated by this module. The 4 independent annunciators are enabled by software command. Annunciator is also controlled by oscillator circuit too. Annunciator output waveform shown in Figure 7.
Internal Oscillator Selected enable1 enable2 Oscillation Circuit enable Buffer
Oscillator enable
MC141803 OSC1 OSC2 External component
Feedback for internal oscillator For external CLK input
Figure 6. Oscillator Circuitry
LCD Driving Voltage Generator This module generates the LCD voltage needed for display output. It takes a single supply input and generate necessary bias voltages. It consists of : 1. Voltage Doubler and Voltage Tripler To generate the Vcc voltage. Either Doubler or Tripler can be enabled. 2. Voltage Regulator Feedback gain control for initial LCD voltage. it can also be used with external contrast control. 3. Voltage Divider Divide the LCD display voltage (VLL2-VLL6) from the regulator output. This is a low power consumption circuit which can save the most display current compare with traditional resistor ladder method. 3. Bias Ratio Selection circuitry Software control of 1/5 and 1/7 bias ratio to match the characteristic of LCD panel. 4. Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. 5. Contrast Control Block Software control of 16 voltage levels of LCD voltage. 6. External Contrast Control By adjusting the gain control resistors connected externally, the contrast can be varied. Refer to the application circuit for details. All blocks can be individually turned off if external voltage generator is employed. 33 Bit Latch / 120 Bit Latch A 153 bit long register which carry the display signal information. First 33 bits are Common driving signals and other 120 bits are Segment driving signals. Data will be input to the HV-buffer Cell for bumping up to the required level. Level Selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell for output signal voltage pump. HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shift-er which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal.
LCD Panel Driving Waveform
The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 7a, 7b and 7c illustrate the desired multiplex scheme. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4
Figure 7a. LCD Display Example "0"
MC141803 3-324
MOTOROLA
TIME SLOT
1
2
3
4
1
2
3
4
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1
COM0
COM1
SEG0
SEG1
Figure 7b. LCD Driving Signal from MC141803
TIME SLOT
1
2
3
4
1
2
3
4
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Seg0-Com0 "OFF" Pixel
Seg0-Com1 "ON" Pixel
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Figure 7c. Effective LCD waveform on LCD pixel
MOTOROLA
MC141803 3-325
Command Description
Set Display On/Off (Display Mode / Stand-by Mode) The Display On command turns the LCD Common and Segment outputs on and has no effect to the annunciator output. This command causes the conversion of data in GDDRAM to necessary waveforms on the Common and Segment driving outputs. The onchip bias generator is also turned on by this command. (Note : "Oscillator On" command should be sent before "Display On" is selected) The Display Off command turns the display off and the states of the LCD driver are as follow during display off : 1. The Common and Segment outputs are fixed at VLL1 (VSS). 2. The bias Voltage Generator is turned off. 3. The RAM and content of all registers are retained. 4. IC will accept new commands and data. The status of the Annunciators and Oscillator are not affected by Display Off command. Set GDDRAM Column Address This command positions the address pointer on a column location. The address can be set to location 00H-77H (120 columns). The column address will be increased by one automatically after a read or write operation. Refer to "Address Increment Table" and command "Set GDDRAM Page Address". Set GDDRAM Page Address This command positions the row address to 1 of 5 possible positions in GDDRAM. Refer to figure 5. Master Clear GDDRAM This command is to clear the 480 byte GDDRAM by setting the RAM data to zero. Issue this command followed by a dummy write command. The RAM for icon line will not be affected by this command. Master Clear Icons This command is used to clear the data in page 5 of GDDRAM which stores the icon line data. Before using this command, set the page address to Page 5 by the command "Set GDDRAM Page Address". A dummy write data is also needed after this "Master Clear Icons" command to make the clear icon action effective. Set Display with Icon Line If 1/32 Mux selected, use this command change to 1/33 Mux for using the Icon LIne. This command can also change Icon Display Mode to Normal Display Mode (1/32 or 1/33 MUX). Set Icon Display Mode This command force the output to the icon display mode. Display on Row 0 to Row 31 will be disabled. Set Icon Line / Annunciator Contrast Level The contrast of the icon line and annunciators in Icon Mode can be set by this command. There are four levels to select from. Set Vertical Scroll Value This command is used to scroll the screen vertically with scroll value 0 to 31. With scroll value equals to 0, Row 0 of GDDRAM is mapped to Com0 and Row 1 through Row 31 are mapped to Com1 through Com31 respectively. With scroll value equal to 1, Row 1 of GDDRAM is mapped to Com0, then Row 2 through Row 31 will be mapped to Com1 through Com30 respectively and Row 0 will be mapped to Com31. Com32 is not affected by this command. Save / Restore GDDRAM Column Address With bit option = 1 in this command, the Save / Restore Column Address command saves a copy of the Column Address of GDDRAM. With a bit option = 0, this command restores the copy obtained from the previous execution of saving column address. This instruction is very useful for writing full graphics characters that are larger than 8 pixels vertically. Set Column Mapping This instruction selects the mapping of GDDRAM to Segment drivers for mechanical flexibility. There are 2 mappings to select: 1. Column 0 - Column 119 of GDDRAM mapped to Seg0-Seg119 respectively; 2. Column 0 - Column 119 of GDDRAM mapped to Seg119-Seg0 respectively. Com32 will not be affected by this command. Detailed information please refer to section "Display Output Description". Set Row Mapping This instruction selects the mapping of GDDRAM to Common Drivers for mechanical flexibility. There are 2 selected mappings: 1. Row 0 - Row 31 of GDDRAM to Com0 - Com31 respectively; 2. Row 0 - Row 31 of GDDRAM to Com31 - Com0 respectively. Com32 will not be affected by this command. See section "Display Output Description" for related information. Set Annunciator Control Signals This command is used to control the active states of the 4 stand alone annunciator drivers. Set Oscillator Disable / Enable This command is used to either disable or enable the Oscillator. For using internal or external oscillator, this command should be executed. The setting for this command is not affected by command "Set Display On/Off" and "Set Annunciator Control Signal". See command "Set Internal / External Oscillator" for more information Set Internal / External Oscillator This command is used to select either internal or external oscillator. When Internal Oscillator is selected, feedback resistor between OSC1 and OSC2 is needed. For external oscillation circuit, feed clock input signal to OSC2 and leave OSC1 open. Set Clock Frequency Use this command to choose from two different oscillation frequency (50kHz or 38.4kHz) to get the 60 Hz frame frequency. With frequency high, 50 kHz clock frequency is preferred. 38.4kHz clock frequency (low frequency) enable for power saving purpose. Set DC/DC Converter On/Off Use this command selects the Internal DC/DC Converter to generate the VCC from AVDD. Disable the Internal DC/DC Converter if external Vcc is provided. Set Voltage Doubler / Tripler Use this command to choose Doubler or Tripler when the Internal DC/DC Converter is enabled. Set Internal Regulator On/Off Choose bit option 0 to disable the Internal Regulator. Choose bit option 1 to enable Internal Regulator which consists of the internal contrast control and temperature compensation circuits.
MC141803 3-326
MOTOROLA
Set Internal Voltage Divider On/Off If the Internal Voltage Divider is disabled, external bias can be used for VLL6 to VLL2. If the Internal Voltage Divider is enabled, the internal circuit will automatically select the correct bias level according to the number of multiplex. Refer to command "Bias Ratio Select". Set Duty Cycle This command is to select 16 mux or 32 mux display. When 16 mux is enabled, the unused 16 common outputs will be swinging between VLL2 and VLL5 for dummy scan purpose and doubler will be used. Set Bias Ratio This command sets the 1/5 bias or 1/7 bias for the divider output. The selection should match the characteristic of LCD Panel. Set Internal Contrast Control On/Off This command is used to turn on or off the intrernal control of delta voltage of the bias voltages. With bit option = 1, the software selection for delta bias voltage control is enabled. With bit option = 0, internal contrast control is disabled. Increase / Decrease Contrast Level If the internal contrast control is enabled, this command is used to increase or decrease the contrast level within the 16 contrast levels. The contrast level starts from lowest value after POR.
Set Contrast Level This command is to select one of the 16 contrast levels when internal contrast control circuitry is in use. Read Contrast Value This command allows the user to read the current contrast level value. With R/W input high (READ), D/C input low (COMMAND) and D7 D6 D5 D4 are equal to 0 0 0 1, the value of the internal contrast value can be read on D0-D3 at the falling edge of CS. Set Temperature Coefficient This command can select 4 different LCD driving voltage temperature coefficients to match various liquid crystal temperature grades. Those temperature coefficients are specified in Electrical Characteristics Tables. Set IDD Reduction Mode On/Off By using this command to reduce the display clock frequency by half. Use in Icon Mode to reduce stand-by current.
MOTOROLA
MC141803 3-327
COMMAND TABLE
Bit Pattern 00000X2X1X0 Command Set GDDRAM Page Address Comment Set GDDRAM Page Address using X2X1X0 as address bits. X2X1X0=000 : page 1 (POR) X2X1X0=001 : page 2 X2X1X0=010 : page 3 X2X1X0=011 : page 4 X2X1X0=100 : page 5 Set one of the 4 available values to the icon and annunciator contrast, using X1X0 as data bits. X1X0=00 (Von = 0.87VDD) X1X0=01 (Von = 0.71VDD) X1X0=10 (Von = 0.61VDD) POR X1X0=11 (Von = 0.55VDD) Set one of the 16 available values to the internal contrast register, using X3X2X1X0 as data bits. The contrast register is reset to 0000 during POR. With D/C pin input Low, R/W pin input high, and D7 D6 D5 D4 pins equal to 0001 at the rising edge of CS, the value of the internal contrast register will be latched out at D3 D2 D1 D0 pins, i.e. X3X2X1X0, at the rising edge of CS. X0=0: Select Voltage Tripler (POR) X0=1: Select Voltage Doubler X0=0 : Col0 to Seg0 (POR) X0=1 : Col0 to Seg119 X0=0 : Row0 to Com0 (POR) X0=1: Row0 to Com31 X0=0: display off (POR) X0=1: display on X0=0: DC/DC Converter off (POR) X0=1: DC/DC Converter on X0=0: Internal Regulator off (POR) X0=1: Internal Regulator on When the application employs external contrast control, the internal contrast control, temperature compensation and the Regulator must be enabled. X0=0: Internal Voltage Divider off (POR) X0=1: Internal Voltage Divider on When an external bias network is preferred, the voltage divider should be disabled. X0=0: Internal Contrast Control off (POR) X0=1: Internal Contrast Control on Internal contrast circuits can be disabled if external contrast circuits is preferred. X0=0 : low frequency (38.4kHz) (POR) X0=1 : high frequency (50kHz) X0=0 : restore address X0=1 : save address Master clear GDDRAM page 1 to 4 Master Clear of GDDRAM page 5. GDDRAM page 5 should be selected and dummy write is required X0=0: set 1/7 bias (POR) X0=1: set 1/5 bias X0=0: normal operation (POR) X0=1: test mode (Note: Make sure to set X0=0 during application)
000011X1X0
Set Icon Line / Annunciator Contrast Level
0001X3X2X1X0
Set Contrast Level
0001X3X2X1X0
Read Contrast Value
0010000X0 0010001X0 0010010X0 0010011X0 0010100X0 0010101X0 0010110X0
Set Voltage Doubler / Tripler Set Column Mapping Set Row Mapping Reserved Set Display On/Off Set DC/DC Converter On/Off Set Internal Regulator On/Off
0010111X0
Set Internal Voltage Divider On/Off
0011000X0
Set Internal Contrast Control On/Off
0011001X0 0011010X0 00110110 00110111 0011100X0 0011101X0
Set Clock Frequency Save/Restore GDDRAM Column Address Master Clear GDDRAM Master Clear Icons Set Bias Ratio Reserved.
MC141803 3-328
MOTOROLA
Bit Pattern 0011110X0 00111110 010X4X3X2X1X0 01100A1A0X0
Command Set Display with Icon Line Set Icon Display Mode Set Vertical Scroll Value Set Annunciator Control Signals
Comment X0=0: set display mode without Icon Line (POR) X0=1: set display mode with Icon Line Power saving icon display mode, Com0 to Com31 will be disabled Use X4X3X2X1X0 as number of lines to scroll. Scroll value = 0 upon POR A1A0=00: select annunciator 1 (POR) A1A0=01: select annunciator 2 A1A0=10: select annunciator 3 A1A0=11: select annunciator 4 X0=0: turn selected annunciator off (POR) X0=1: turn selected annunciator on X0=0: 1/32 duty and tripler enabled (POR) X0=1: 1/16 duty and doubler enabled X0=0: Normal Mode X0=1: IDD Reduction Mode X1X0=00 : 0.00% (POR) X1X0=01 : -0.18% X1X0=10 : -0.22% X1X0=11 : -0.35% X0=0: Decrease by one level X0=1: Increase by one level (Note: increment/decrement wraps round among the 16 contrast levels. Start at the lowest level when POR.
0110100X0 0110101X0 011011X1X0
Set Duty Cycle Set IDD Reduction Mode Set Temperature Coefficient
0111000X0
Increase / Decrease Contrast Value
0111001X0 0111010X0 0111011X0
Reserved Reserved Reserved X0=0: normal operation (POR) X0=1: test mode select (Note: Make sure to set X0=0 during application) X0=0: Internal oscillator (POR) X0=1: External oscillator. Internal oscillator circuit is automatically enabled if resistors are placed at OSC1 and OSC2. For external oscillator, simply feed clock in OSC2.
0111100X0 0111101X0
Reserved Set Internal / External Oscillator
0111110X0 0111111X0
Reserved Set Oscillator Disable / Enable X0=0: oscillator disable (POR) X0=1: oscillator enable. This is the master control fro oscillator circuitry. This command should be issued after the "External / Internal Oscillator" command. Set GDDRAM Column Address. Use X6X5X4X3X2X1X0 as address bits.
1X6X5X4X3X2X1X0
Set GDDRAM Column Address
Data Read / Write
To read data from the GDDRAM, input High to R/W pin and D/C pin. Data is valid at the falling edge of CS. And the GDDRAM column address pointer will be increased by one automatically. To write data to the GDDRAM, input Low to R/W pin and High to D/C pin. Data is latched at the falling edge of CS. And the GDDRAM column address pointer will be increased by one automatically. No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the "Commands Required for R/W Actions on RAM" Table)
MOTOROLA
MC141803 3-329
Address Increment Table (Automatic)
D/C 0 0 1 1 R/W 0 1 0 1 Comment Write Command Read Command Write Data Read Data Address Increment No No Yes Yes *1 *2 Remarks
Address Increment is done automatically data read write. The column address pointer of GDDRAM*3 is affected. Remarks : *1. Refer to the command "Read Contrast Value". *2. If write data is issued after Command Clear RAM, Address increase is not applied. *3. Column Address will be wrapped round when overflow.
Power Up Sequence (Commands Required)
Command Required Set Clock Frequency Set Oscillator Enable Set Annunciator Control Signals Set Duty Cycle Set Bias Ratio Set Interna DC/DC Converter On Set Internal Regulator On Set Temperature Coefficient Set Internal Contrast Control On Increase Contrast Level Set Internal Voltage Divider On Set Segment Mapping Set Common Mapping Set Vertical Scroll Value Set Display On POR Status Low Disable Annunciator all Off 1/32 duty 1/7 bias Off Off TC=0% Off Contrast Level = 0 Off Seg. 0 = Col. 0 Com. 0 = Row 0 Scroll Value = 0 Off Remarks *1 *1 *1 *1 *1 *1 *1 *1, *3 *1, *3 *1, *2, *3 *1 Remarks : *1 -- Required only if desired status differ from POR. *2 -- Effective only if Internal Contrast Control is enabled. *3 -- Effective only if Regulator is enabled.
Commands Required for Display Mode Setup
Display Mode Display Mode Commands Required Set External / Internal Oscillator, Set Oscillator Enable, Set Display On. Set External / Internal Oscillator, Set Oscillator Enable, Set Annunciator Control Signal. Set Display Off, Set Oscillator Disable. Set External Oscillator, Set Annunciator Control Signal, Set Display Off, Set Oscillator Enable. Set Internal Oscillator, Set Annunciator Control Signal, Set Display Off, Set Oscillator Enable. (0111101X0)* (01111111)* (00101001)* (0111101X0)* (01111111)* (01100A1A0X0)* (00101000)* (01111110)* (01111011)* (01100A1A0X0)* (00101000)* (01111111)* (01111010)* (01100A1A0X0)* (00101000)* (01111111)*
Annunciator Display
Standby Mode 1. Standby Mode 2.
Standby Mode 3.
Other Related Command with Display Mode : Set Duty Cycle, Set Column Mapping, Set Row Mapping, Set Vertical Scroll Value. Commands Related to Internal DC/DC Converter : Set Oscillator Disable / Enable, Set Internal Regulator On/Off, Set Duty Cycle, Set Temperature Coefficient, Set Internal Contrast Control On/ Off, Increase / Decrease Contrast Level, Set Internal Voltage Divider On/Off, Set Bias Ratio, Set Display On/Off, Set Internal / External Oscillator, Set Contrast Level, Set Voltage Doubler / Tripler, Set 33 Mux Display Mode, Set Icon Display Mode * No need to resend the command again if it is set previously.
MC141803 3-330
MOTOROLA
Commands Required for R/W Actions on RAM
R/W Actions on RAMs Read/Write Data from/to GDDRAM. Commands Required Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data Save/Restore GDDRAM Column Address. Dummy Read Data Master Clear GDDRAM Dummy Write Data (000X4X3X2X1X0)* (1X6X5X4X3X2X1X0)* (X7X6X5X4X3X2X1X0) (0011010X0) (X7X6X5X4X3X2X1X0) (00110110) (X7X6X5X4X3X2X1X0)
Save/Restore GDDRAM Column Address. Increase GDDRAM Address by One Master Clear GDDRAM
* No need to resend the command again if it is set previously. Display Output Description This is an example of output pattern on the LCD panel. Figure 8b and 8c are data map of GDDRAM and the output pattern on the LCD display with different command enabled.
COM0 Content of GDDRAM PAGE 1 Upper Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A Lower Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A PAGE 2 Upper Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C Lower Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C PAGE 3 Upper Nibble 0 0 0 0 F F F F 0 0 - - - - - - - - - F F 0 0 0 0 F F F F Lower Nibble F F F F 0 0 0 0 F F - - - - - - - - - 0 0 F F F F 0 0 0 0 PAGE 4 Upper Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0 Lower Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0 PAGE 5 Upper Nibble 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 Lower Nibble 0 0 0 1 1 1 0 0 0 0 - - - - - - - - - 0 0 0 0 1 1 1 0 0 0
COM31 COM32 SEG0 SEG119
Figure 8b
Figure 8a
Column remap disable Row re-map disable
Column remap enable Row re-map disable
Column remap disable Row re-map enable
Column remap disable Row re-map disable Scroll Value = 31
Figure 8c. Examples of LCD display with different command enabled
MOTOROLA
MC141803 3-331
MC141803T TAB PACKAGE DIMENSION (1 OF 2) 98ASL10017A ISSUE 0 DO NOT SCALE THIS DRAWING
Copper Side
MC141803 3-332
MOTOROLA
MC141803T TAB PACKAGE DIMENSION (2 OF 2) 98ASL10017A ISSUE 0 DO NOT SCALE THIS DRAWING
MOTOROLA
MC141803 3-333
Application Circuit 32/33 MUX Display with Analog Circuitry enabled, Tripler enabled and 1/7 bias
DVDD 0.1F
AVDD 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
DVSS
DVDD
AVDD
AVSS
VLL2 VLL3 DUM2 DUM1 VLL4
VLL5
VLL6
VCC
RES D/C CMOS MPU/ MCU with Parallel Interface CS CE R/W D0~D7 OSC2 OSC1 C+ C- VF MC141803
COM0 to COM32
SEG0 to SEG119
To LCD Panel
Annun 0-3 and BP
VR C2P C2N C1P
C1N
EPROM
RAM 1M 0.1F
760k 0.1F 4.7F 0.1F
560pF 200k
Remark : 1. VR and VF can be left open for Regulator Disable. 2. CS pin low at Standby Mode.
MC141803 3-334
MOTOROLA
Application Circuit 16 MUX Display with Analog Circuitry enabled, Tripler Disabled and 1/5 bias
DVDD 0.1F
AVDD 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
DVSS
DVDD
AVDD
AVSS
VLL2 VLL3 DUM2 DUM1 VLL4
VLL5
VLL6
VCC
RES D/C CMOS MPU/ MCU with Parallel Interface CS CE R/W D0~D7 OSC2 OSC1 C+ C- VF MC141803
COM0 to COM32
SEG0 to SEG119
To LCD Panel
Annun 0-3 and BP
VR C2P C2N C1P
C1N
EPROM
RAM External Clock 0.1F
760k 0.1F 560pF 200k 4.7F
Remark : 1. VR and VF can be left open for Regulator Disable. 2. CS pin low at Standby Mode.
MOTOROLA
MC141803 3-335
Application Circuit 16/32/33 MUX Display with Analog Circuitry disabled
DVDD 0.1F
AVDD 0.1F
VCC
DVSS
DVDD
AVDD
AVSS
VLL2 VLL3 DUM2 DUM1 VLL4
VLL5
VLL6
VCC
RES D/C CMOS MPU/ MCU with Parallel Interface CS CE R/W D0~D7 OSC2 OSC1 C+ CVF VR C2P C2N MC141803
COM0 to COM32
SEG0 to SEG119
To LCD Panel
Annun 0-3 and BP
C1P
C1N
EPROM
RAM External Clock
Remark : 1. VR and VF can be left open for Regulator Disable. 2. CS pin low at Standby Mode.
MC141803 3-336
MOTOROLA

▲Up To Search▲

Price & Availability of MC141803

	To Download MC141803 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .